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As a result, the cell layout can be organized as a simple linear array of storage cells with a compare/exchange cell between every other pair of adjacent storage cells. Also, it is quite easy to accommodate the sorting of more than N items by making RESST chips cascadable. Providing cascadability just involves buffering the right-hand outputs and inputs of 30 MICHAEL J. CAREY, PAUL M. HANSEN, AND CLARK D. 2. Example of Parallel Bubblesort Operation. the last storage cell in the array and providing off-chip connections for them.

C. D. Thompson, " A Complexity Theory for VLSI," Report No. CMU-CS- 80-140, Dept. of Comp. , Pittsburgh, Penn. (August, 1980). 18. J. Vuillemin, " A Combinatorial Limit to the Computing Power of VLSI Circuits," Procs. 21st Ann. Symp. Foundations of Computer Science, pp. 294-300 (Oct. 13-15, 1980). 19. A. Weinberger, "Large Scale Integration of MOS Complex Logic: A Layout Method," IEEE Jnl. of Solid State Circuits SC-2(4) pp. 182-190 (Dec. 1967). Sorting Records in VLSI Michael J. Carey Paid M. Hansen Clark D.

Why Systolic Architectures? Computer Magazine 15(1): 37-46, January, 1982. T. and Leiserson, CE. Systolic Arrays (for VLSI). In Duff, I. S. and Stewart, G. W. (editors). Sparse Matrix Proceedings 1978, pages 256-282. Society for Industrial and Applied Mathematics, 1979. A slightly different version appears in Introduction to VLSI Systems by C. A. Mead and L. A. 3. J. A. The Theory of Error-Correcting Codes, North-Holland, Amsterdam, Holland, 1977. A. A. Introduction to VLSI Systems. Addison-Wesley, Reading, Massachusetts, 1980.

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